Time-interleaved Analog-to-Digital Converters (TIADCs) have received considerable attention in the recent past for applications that require very high sample rates, i.e., sample rates that cannot be provided by a single Analog to Digital Converter (ADC) core. In a TIADC system, a faster ADC is obtained by combining two or more slower ADCs operating in parallel. Ideally, the slower ADCs should each have the same offset, the same gain, and the same uniform sample instants. In practice, however, due to fabrication errors, component mismatches, temperature variations, mechanical strain, environmental perturbations, etc., this requirement is difficult to achieve. The resulting errors degrade the performance of the TIADC system, thus making the estimation and correction of these errors imperative to improve performance.
Various interleave error correction techniques are known. However, those have been observed to have limitations in practice.